Speaker: Dr. Chen Donglong

Time: 3:00-4:00p.m., 6 May 2020 (Wed)

Venue: Tencent Meeting 663 061 574

Language: English

Abstract:

Rotation Region Proposal Networks (RRPN) are used to generate rotated proposals with the information of text angle. Based on RRPN, the precision of arbitrary oriented Scene Text Detection (STD) has been improved significantly. However, the computational complexity of RRPN inference is relatively high compared with other methods, which makes it difficult for massive deployment.

In this paper, a heterogeneous system constituted by Filed Programmable Gate Array (FPGA) and CPU for RRPN based scene text detection is proposed. By fully exploiting the parallel and pipelined merits in the algorithm, the majority of the computation tasks are performed in FPGA, which relives the computation workload of CPU. The fast 2D Winograd algorithm and block floating point are utilized to enhance the computation efficiency while maintaining a relatively high precision. The implementation results show that the peak performance of the MAC array in the proposed architecture reaches 1638.4 GOPS and the energy efficiency achieves 73.6 GOPS/W. The throughput of the proposed FPGA-CPU heterogeneous system achieves 40 times and 1.4 times improvements compared with CPU and GPU, respectively. Moreover, the compressive operating expense ratio (OpEx) of pure CPU, GPU, and the proposed system is 80.8:2.4:1, which indicates that it is suitable for massive deployment.

About the Speaker

Dr Chen Donglong  is an Assistant Professor in Data Science at DST, UIC. He received the PhD degree in electronic engineering from the City University of Hong Kong, Hong Kong, China, in 2015. He worked as an engineer with Huawei Technology Co., Ltd., from 2015 to 2017. From 2017 to 2019, he worked as a senior engineer with Tencent Technology (Shenzhen) Co., Ltd., China. His research interests include deep learning algorithm acceleration in hardware, cryptographic hardware and high-speed digital system design, especially in field programmable gate array (FPGA).